In a power semiconductor package structure, a power chip is first assembled to a leadframe using solder material, and then a wire bonding is performed. However, the wire bonding method does not contribute to dissipating the heat of the components, and the reliability is also poor. At present, in the industry, the power chip is mounted on the substrate by the solder material using a flip-chip technique. Although this method can improve electrical conductivity and thermal conductivity of the package structure, when a large current passes through the solder material, the solder material that is not resistant to high current will generate hole-shaped defects (kirkendall void) in the material structure, resulting in a breakdown between the upper and lower components connected by the solder material after long-term use or during a reliability testing process.
Therefore, development of a package structure with high heat dissipation efficiency and high current resistance is desirable.